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Wide Input Range High Performance Synchronous Buck Switching Regulator
POWER MANAGEMENT Description
SC4611 is a high performance synchronous buck controller that can be configured for a wide range of applications. The SC4611 utilizes synchronous rectified buck topologies where high efficiency is the primary consideration. It is optimized for applications involving multiple and redundant convertors connected together. The star tup is asynchronous, which keeps the lower side FET off during soft start. This is a desired feature when a convertor is turned on with a preset external voltage or pre-bias voltage already present across its output. With the lower FET off, external bus is not discharged which avoids latch-up of modern ASIC circuits. SC4611 comes with a rich set of features like regulated Vcc supply, soft start, power-good signaling, high current gate drivers, bootstrapped supply for driving high side Nchannel MOSFETs, shoot through protection, frequency synchronization and the option for overvoltage crowbar. It also features multi mode overload protection that includes continuous current limiting, hiccup mode followed by latch off. The user has the option of bypassing the hiccup mode and latch off the output if required.
SC4611
Features
Wide input range, 4.5 to 30V Output voltage as low as 0.5V 2A output drive capability Asynchronous start up mode Multimode overcurrent protection with current limit, hiccup mode and latched shutdown Overvoltage crowbar protection Power OK signal Programmable frequency up to 1 MHz with external synchronization -40 to +85 degree C operating temperature Thermal shutdown Small package TSSOP-20
Applications
Distributed power architectures Telecommunication equipment Servers/work stations Mixed signal applications Paralleled synchronous buck convertors Base station power management
Typical Application Circuit
VIN (30V MAX)
QH Cin Lout Rcs QL
4 5 17 20 14 13
VOUT (0.5V MIN)
VIN BD I AVC C
BS T GDH PH
3 2 1 19 7 6 11 15 18 10
Cout
S S /S H OS C S YN C CLM E AO FB
SC4611
P VC C
GDL CS+ CSOVP AG N D PGND P OK
Rclset
RTN
RT
16 12 9 8
RTN
Revision: November 10, 2004
1
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SC4611
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter BST to PGND VIN and BDI to PGND PVCC, AVCC to PGND PGND to AGND BST to PH GDH to PH, GDL to PGND All Other Pins to AGND GDH, GDL Source or Sink Current Storage Temperature Range Junction Temperature Lead Temperature (Soldering) 10 Sec.
Symbol VBSTMAX VINMAX AVCCMAX
Maximum 37 30 7 0.3 -0.3 to 7
Units V V V V V V V A C C C
VGDHMAX, VGDLMAX
PVCC +0.3 AVCC +0.3
IGDHMAX, IGDLMAX TSTGMAX TJMAX
2 -60 to +150 -40 to +125 260
Electrical Characteristics
Unless specified: TA = TJ = -40 to +85C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V
Parameter Power Supply AVCC PVCC Operating Current Quiescent Current Undervoltage Lockout Start Threshold UVLO Hysteresis Soft Start/Shut Down Charge Current Discharge Current Disable Threshold Voltage Disable Low to Shut Dow n
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(1)
Symbol
Test Conditions
Min
Typ
Max
Unit
AVCC PVCC ISUPPLY IQUI
VIN > 5.5V VIN > 5.5V No load on GDH and GDL pins SS/SH = 0V
4.5 4.5
6 6 7 4
6.5 6.5 10 6
V V mA mA
VUVLO
AVCC Rising
4.0
4.2 0.16
4.4
V V
ISSC ISSD
4
7 0.5 0.5 50
10
A mA V nS
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SC4611
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = TJ = -40 to +85C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V
Parameter Oscillator Frequency Range Frequency Peak to Peak Ramp Voltage(1) SY NC Input High Pulse Width SY NC Rise/Fall Time SY NC Frequency Range SY NC High/Low Threshold Error Amplifier Feedback Voltage Input Bias Current
(1)
Symbol
Test Conditions
Min
Typ
Max
Unit
Fsw Fsw VRAMP TSYNC RT = 15K
150 550 625 3.0 100
1000 700
kHz kHz V nS
50 Fsw VSYNC 2.0 Fsw +15%
nS kHz V
VFB
TA = 25 Deg C
0.493
0.5 0.2 3 90
0.507
V A MHz dB mA
Unity Gain Bandwidth (1) Open Loop DC Gain (1) Output Source/Sink Current Current Sense Comparator CS- pin offset current (ILIM ADJ) Current limit sense threshold Current limit hysteresis Power Good and Overvoltage Protection FB Level for Output High Sense Hysteresis (1) FB Level for Output Low Sense Hysteresis (1) PWR OK Output Low Level OVP Trip Reference VPOK VOVP IPOK = 0 0.475 VHTH 0.42 VLTH 0.52 ICSVCL RT = 15K Rclset = 1K 66 66 IEAO
+ 10
82 82 30
98 98
A mV %
0.55 6 0.45 6 0.2 0.5
0.58
V mV
0.48
V mV V
0.525
V
(1) Guaranteed by design. Not tested in production.
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SC4611
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = TJ = -40 to +85C, Vin = 12V, PVCC = AVCC = 6V, Fsw = 625 kHz, SS/SH = 5V
Parameter Duty Cycle Maximum Duty Cycle
Symbol
Test Conditions
Min
Typ
Min
Units
Dmax
Fsw = 150 kHz Fsw = 1 MHz
90 80 150
% % nS
Minimum Pulse Width (1) Output Gate Drive ON-Resistance (H) Gate Drive OFF-Resistance (H) Gate Drive ON-Resistance (L) Gate Drive OFF-Resistance (L) Rise Time Fall Time Dead Time Between Drive Signals (1)
Tpulsemin
RONGDH ROFFGDH RONGDL ROFFGDL Trise Tfall
ISOURCE = 20 mA ISINK = 20 mA ISOURCE = 20 mA ISINK = 20 mA COUT = 2000 pF COUT = 2000 pF
2 1 2 1 15 15 30
nS nS nS
NOTES: (1) Guaranteed by design. Not tested in production. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required
Pin Configuration
TOP VIEW
PH GDH BST VIN BDI CSCS+ FB EAO POK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PVCC GDL PGND AVCC SYNC AGND SS/SH OSC CLM OVP
Ordering Information
Part Number SC4611ITSTRT
(2)
P ackag e TSSOP-20 (1)
Temp. Range -40C to +85C
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free device. This product is fully WEEE and RoHS compliant.
(20 Pin TSSOP)
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SC4611
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name PH GDH BST VIN BD I C SC S+ FB EAO POK OVP C LM OSC SS/SH AGND SYNC AVCC PGND GDL PVC C Pin Function Switching junction of high side Mosfet source and low side Mosfet drain. Gate drive output for high side N-Channel MOSFET. Boost capacitor connection for the high side gate drive. Connect an external capacitor and a diode as shown in the Typical Application Circuit. Input supply voltage. Base drive for AVCC/PVCC regulator. Inverting input for the current sense comparator Non inverting input for the current sense comparator Feedback input pin.The reference level is 0.5V Error amplifier output for compensation. Open drain of power good output. Overvoltage protection input. The reference level is 0.5V Current Limit Mode select input. Connect to AVCC to enable hiccup or connect to AGND to bypass hiccup mode. Connect a resistor to AGND for programming the oscillator frequency. Soft start pin. Hold low to shutdown the device. Analog signal ground. Oscillator synchronization pin. Connect to AGND if not used. Supply voltage for analog circuitry. Power ground. Gate drive output for the low side N-Channel MOSFET. Supply voltage for output drivers.
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SYNC
IN RAMP
SYNC CLK
OSC
-
OSC & SYNC
+
-
+
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POK BANDGAP 0.55V UVLO
VS REF OUT
VIN OV MONITOR
+ -
FB
POWER MANAGEMENT Block Diagram - SC4611
AVCC
VS VBG
+
0.45V AVCC
+
BDI
EA
+
SHDN
+
FB
-
UV MONITOR
SHDN SS CLM ILIM + OUT
7 uA SS CLM
PVCC SS-SEQ ILIM COMP
-
4R
R ENABLE SR LATCH_1
R FB OUTL S Q QB OUTH
ILIM ADJ CS+ CSBST DRIVER GDH PH PVCC DRIVER GDL
6
DRV LOGIC SR LATCH_2
R QB S Q IN
AGND
0.5V
+
+
OVP PW M COMP
-
OVP COMP
VEA
PGND FB
+
0.5V EAO
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SC4611
SC4611
POWER MANAGEMENT Applications Information
INTRODUCTION INTRODUCTION The SC4611 is designed to control and drive N-Channel MOSFET synchronous rectified buck convertors. The switching frequency is programmable to optimize design. The SC4611 switching regulator section features external current sensing and provides a hiccup mode overcurrent protection followed by a latched shutdown. It is also optimized for multiple convertors operating in parallel redundant mode. POWERING CONTROLLER POWERING THE CONTROLLER Supplies VIN, PVCC and AVCC from the input source are used to power the SC4611. The VIN supply provides the bias for the internal reference and UVLO circuitry. The AVCC supply provides the bias for the oscillator, PWM switcher, voltage feedback, current sense and the Power OK circuitry. PVCC is used to drive the low and high side MOSFET gates. An external PNP transistor can be set up as a linear regulator to generate well regulated AVCC and PVCC as shown in the Typical Application Circuit. The maximum current into the BDI pin should be limited to 5 mA under all conditions. For example if an external PNP transistor is used with Vin less than 7V, the BDI pin will saturate and pull down the Vin input. A series resistor between the base of the external PNP transistor and the BDI should be used to limit the current into the BDI pin. The VCC pins have an absolute maximum rating of 7V. If maximum VIN is less than 7V it may be connected directly to AVCC and PVCC, leaving the BDI pin open. START UP SEQUENCE ART Start up is inhibited until AVCC input reaches its UVLO threshold. The UVLO limit is 4.2V typical. The power up sequence is initiated by a 7 uA current source charging the soft start capacitor connected to the SS pin. When the SS pin reaches 1V, the converter will start switching. The reference input of the error amplifier is ramped up with the soft-start signal, level shifted down by 1V. Initially only the high side driver is enabled. Keeping the low side MOSFET off during start up is useful where multiple convertors are operating in parallel. It prevents forward conduction in the freewheeling MOSFET which might otherwise cause a dip in the common output bus.
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When the SS pin reaches 2V, the low side MOSFET will begin to switch and the convertor is fully operational in the synchronous mode. The reference input of the error amplifier is released and the SS pin is pulled up to AVCC. The soft start duration is controlled by the value of the SS cap. If the SS pin is pulled below 0.5V, the device is disabled and draws only 4 mA current. Note that the SS pin threshold for soft-start is supply dependant and defined above for AVCC = 6V. If AVCC is lower, the threshold should be reduced proportionately, i.e. SS enable threshold will be 0.375V when AVCC = 4.5V. GATE DRIVERS The low side gate driver is supplied from PVCC and provides a peak source/sink current of 2A. The high side gate drive is also capable of sourcing and sinking peak currents of 2A. Protection logic provides a 30 nS dead time to ensure both the upper and lower MOSFETs will not turn on simultaneously and cause a shoot through condition. The high side MOSFET gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper MOSFET will approximately equal 6V (12V-VCC). If the external 12V supply is not available, a classical bootstrap technique can be implemented from the PVCC supply. A bootstrap capacitor is connected from BST to Phase while PVCC is connected through a diode (Low VF Schottky or ultrafast diode) to the BST. This will provide a gate to source voltage approximately equal to the VCC-Vdiode drop. OSCILLAT OSCILLATOR The switching frequency fsw of the SC4611 is set by an external resistor using the following formula:
RT
=
9375 Fsw
RT is in kOhm and fsw is in kHz. This relation is a first order approximation of the more complex relationship between RT and Fsw. The oscillator can be synchronised to an external clock that is nominally faster than the internal frequency set by ROSC. The external voltage level applied should be lower than AVCC of the device.
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SC4611
POWER MANAGEMENT Applications Information (Cont.)
OVERCURRENT PROTECTION VERCURRENT PRO SC4611 includes a precision current sense comparator for maximum flexibility. The current feedback can be taken either from the output inductor for lossless sensing and better efficiency, or from a series resistor for improved accuracy. An offset current of 1.225/RT pulls up on the CSpin, providing an offset voltage across a resistance on the input to this pin. The offset voltage should be set to > 50 mV. A voltage across the current sense resistor of greater than this value will produce a current limit pulse. There is 30% hysteresis on the offset current. Since the offset current into CS- is set by RT, the current limit needs to be adjusted if the frequency setting is changed. Note that the operational limit for CS- and CS+ inputs is 0.5V below the AVCC supply. The first stage of protection against overloads is peak current limiting on a pulse by pulse basis. Once an overload is sensed, the high side FET is turned off and held low for the rest of the cycle. This provides peak current limiting on a pulse by pulse basis. The final response of the device to a severe overload can be programmed using the CLM pin. If the CLM pin is connected to AVCC, the hiccup mode is enabled. A soft-start/hiccup cycle is initiated if 64 current limit pulses are detected in any counting period of 128 oscillator cycles. The SS capacitor is discharged with a 0.6 mA sink current. There will be 3 dummy soft-starts, i.e. the SS pin will be pulled up to 2V and then discharged to < 1V. This will be repeated 7 times, and if the overload persists the part will be latched off on the eighth attempt. Reset is by recycling the input power. During the hiccups, the device will operate in asynchronous mode, just as in the powerup sequence. In some cases the repeated soft start cycling may not be desirable, depending on the nature of load. If the CLM is taken low to AGND, the hiccup mode will be skipped. When an overcurrent event occurs a comparator detects it and puts out a signal into a latch counter. The counter keeps track of the number of current-limit pulses and is reset after every 128 oscillator cycles. If 64 current-limit pulses are detected in any counting period of 128 cycles, the SS pin will be pulled low. The device is latched off until power is recycled. The CLM pin should be connected to either AGND or AVCC at all times and should not be left open. POWER MONITOR POWER OK MONITOR The power OK circuitry monitors the FB input of the error amplifier. If the voltage on this input goes above 0.55V or below 0.45V the POK pin is pulled low. The POK is an open drain output and is held low until the end of the startup sequence i.e. till the SS pin reaches 2V or more. PRO VERVOLT OVERVOLTAGE AND THERMAL PROTECTION The overvoltage input can be connected to OVP pin with a low reference of 0.5V. If this feedback exceeds the reference the low side FET is continuously gated on to crowbar the input VIN. This feature may be used to protect the load from possible overvoltage in case the high side FET fails and shorts. The crowbar current in the power devices is limited only by the source of VIN. SC4611 also incorporates thermal protection. If the chip temperature exceeds approximately 150 Deg C, the outputs are shutdown. ERROR ERROR AMPLIFIER DESIGN SC4611 is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below:
V 1 + sESRCC G ( s) = IN x VD L V + s2 LC 1+ s S R L
where, VIN - Input voltage L - Output inductance ESRC - Output capacitor ESR VS - Peak to peak ramp voltage RL - Load resistance C - Output capacitance
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SC4611
POWER MANAGEMENT Applications Information (Cont.)
The classical Type III compensation network can be built around the error amplifier as shown below
C3 C2 R1 + Vref R3 R2 C1
The design guidelines are as following: 1. Set the loop gain crossover frequency wC for given switching frequency. 2. Place an integrator in the origin to increase DC and low frequency gains. 3. Select wZ1 and wZ2 such that they are placed near wO to dampen peaking; the loop gain has -20 dB rate to go across the 0 dB line for obtaining a wide bandwidth. 4. Cancel wESR with compensation pole wP1 (wP1 = wESR ). 5. Place a high frequency compensation pole wP2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with the adequate phase lag at wC. LAY FOR SC461 PCB LAYOUT FOR SC4611 Careful attention to layout requirements is necessary for successful implementation of the SC4611 PWM controller. High switching currents with fast rise and fall times are present in the application and their effect on ground plane voltage differentials must be understood and minimized. A good layout with minimum parasitic loop areas will
Figure 1. Voltage Mode Buck Converter Compensation Network The transfer function of the compensation network is as follows:
where,
s s )(1 + ) I Z1 Z 2 GCOMP ( s ) = s (1 + s )(1 + s ) P1 P2 (1 +
Z1 =
1 , R2C1
Z 2 =
1 (R1 + R3 )C2
I =
1 , R1(C1 + C3)
P1 =
1 , R3C2
P2 =
1 CC R2 1 3 C1 + C3
a) reduce EMI b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. LAYOUT GUIDELINES LAY
T
Z1 o
Loop gain T(s) Z2
Gd 0dB
c p1 p2
In the following QT and QB denote the high side and low side MOSFETs respectively. 1) A ground plane should be used. The number and position of ground plane interruptions should be minimised so as not to compromise ground plane integrity. Isolated or semiisolated areas of the ground plane may be deliberately introduced to constrain ground currents into particular paths, such as the output capacitor or the QB source.
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ESR
Figure 2. Simplified asymptotic diagram of buck power stage and its compensated loop gain.
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SC4611
POWER MANAGEMENT Applications Information (Cont.)
2). The high power, high current parts of the circuit should be laid out first. The on time loop formed by the input capacitor Cin, the high side FET QT, the output inductor and the output capacitor bank Cout must be kept as small as possible. Another loop area to minimise is formed by low side FET QB, the output inductor and the output capacitor bank Cout during the off period. These loops contain all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. 3). The connection between the junction of QT, QB and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. The top FET gate charge currents flow in this trace. 4) The output capacitor Cout should be located as close to the load terminals as possible. Fast transient load currents are supplied by Cout and connections between Cout and the load must be kept short with wide copper areas to minimize inductance and resistance. This will improve the transient response to step loads. 5) The SC4611 is best placed over a quiet ground plane area. Avoid pulse currents of the Cin, QT, QB loop flowing in this area. This analog ground plane should be connected to the power ground plane at a "quiet" point near the input capacitor. Under no circumstance should it be returned to a point inside the Cin, QT, QB, Cout power ground loops. 6) The SC4611 AGND pin is connected to the separate analog ground plane with minimum lead length . All analog grounding paths including decoupling capacitors, feedback resistors, compensation components, and current-limit setting resistors should be connected to the same plane.
3.3V/10A Evaluation Board Schematic
J1 VIN L1 SHORT T P2 C1 R2
3.3V
10-15V Vin to 3.3V/10A 300 kHz Reference Design With SC4611
VDC R1 220 uF 6612 1R R3 T P5 GDL TP14 R6 2R T P6 R8 2R N/U 6670 Q3 Q4 6670 TP15 R5 .01R/1W C5 390 uF C6 390 uF C7 390 uF C8 10 uF C9 10 uF Q1 T P1 N/U Q2 L2 2.2 uF T P3 .01R/1W R4 T P4 VOUT J3
220 uF
C2
C3 2.2 uF
C4 2.2 uF
GDH PH
J2 RTN
R7 1K Q5 3906 J6-3 SS
J4 RTN VOUT
AVCC R9 T P7 PVCC 5R R10 10K C10 47 nF R14 R15 R11 30.1K R12 10K R13 1K T P8 CLM 12 11 R17 R16 20K R18 10R
J5-1
1.62K
1.62K
N/U
RTN J5-3
OVP 20 19 18 17 16 15 14 SYNC 4148 13 1 uF R19 RED D2 +S TP12 TP13 R21 10K VFB C14 100 pF T P10 C15 10 nF N/U 33.2K C12 R24 2.2 nF R23 TP11 1.78K R25 10R -S R22 249R 2K
P VC C
AVC C
S YN C
PGND
AG N D
O SC
GDL
C S + S S /S H
J6-4
C11 R20 D1 D3 1K N/U VGG BST
U1
GDH
10
1
2
3
4
5
6
7
8
9
POK
E AO
SC4611ITSTR
BD I VI N CS-
BS T
PH
FB
CLM
O VP
J5-2
J6-1
CST P9
CS+
C16 J6-2 RTN 100 uF
C17 10 uF 100 uF
C13 C18 C19 10 uF C20 N/U C21 N/U 1 nF
EAO
R26
J5-4
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SC4611
POWER MANAGEMENT Outline Drawing - TSSOP-20
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 1 2 3 2X N/2 TIPS E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .006 .002 .042 .031 .007 .012 .007 .003 .251 .255 .259 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 20 8 0 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.20 0.09 6.40 6.50 6.60 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 20 0 8 0.10 0.10 0.20
e/2 B D A2 A
aaa C SEATING PLANE
C bxN
A1 bbb C A-B D GAGE PLANE 0.25
H c L (L1) DETAIL
01
SIDE VIEW
NOTES: 1.
SEE DETAIL
A
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). -HTO BE DETERMINED AT DATUM PLANE
2. DATUMS -A- AND -B-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AC.
Land Pattern - TSSOP-20
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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